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STA027
SBC CODEC
PRODUCT PREVIEW
Features

Fully Integrated SBC Encoder And Decoder Operating Modes: - SBC encoder mode (PCM In/Serial Output) - PCM input: 16, 32, 44.1, 48kHz - Channel Mode: Mono, Dual, - Stereo - Subbands: 4 OR 8 - Allocation Methods: - Loudness/SNR - SBC Decoder Mode - Serial Input - PCM Output: 16, 32, 44.1, 48kHz Digital Volume Bass & Treble Control

Serial Bitstream Input/output Interface up to 2Mbit/s Easy Programmable ADC Input Interface Serial PCM Output Interface (I2S and other Formats) PLL for Internal Clock and for Output PCM Clock Generation I2C Control Bus

Low Power 2.4V CMOS Technology with 3.3V Tolerant and Capable I/O
Applications

bluetooth AV Applications
DVD Wirless Speaker Options
m o .c U t4 e e h S ta a .D w w w
TQFP64

Wireless Audio Dongle PC Wireless Speakers
Generic Compressed Audio LinkS Wireless Headphone/Headsets
Description
STA027 is a fully integrated SBC codec targeting wireless audio transmission such as DVD rear channels wireless speakers, USB dongle, PC wireless speakers. The device is fully controllable through a standard I2C bus.
Compression Engine
SBC
The SBC Subband Coding engine can be used when high quality audio is required in wireless applications (such as Bluetooth). SBC is an audio coding system specially designed for Bluetooth AV applications to obtain high quality audio at medium bit rates, and having a low computational complexity. SBC uses 4 or 8 subbands, adaptive bit allocation algorithm, and simple adaptive block PCM quantizers..
Order codes
Part number STA027 Package TQFP64
September 2005
CD00066274
om .c 4U et he aS at .D w w w
Packing Tube Rev 1 1/44
www.st.com 44
STA027
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical bluetooth wireless audio application . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pins description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Host register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 Version registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 5.1.2 5.1.3 VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IDENT : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SOFT_VERSION : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
PLL_AUDIO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . 16
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 PLL_AUDIO_PEL_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL_AUDIO_PEH_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL_AUDIO_NDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PLL_AUDIO_XDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL_AUDIO_MDIV_192 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PLL_AUDIO_PEL_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL_AUDIO_PEH_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL_AUDIO_NDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL_AUDIO_XDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.10 PLL_AUDIO_MDIV_176 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3
PLL_SYSTEM_CONFIGURATION registers description . . . . . . . . . . . . . . . 19
5.3.1 5.3.2 5.3.3 PLL_SYSTEM_PEL_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PLL_SYSTEM_PEH_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PLL_SYSTEM_NDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 PLL_SYSTEM_XDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PLL_SYSTEM_MDIV_50 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PLL_SYSTEM_PEL_42_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PLL_SYSTEM_PEH_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PLL_SYSTEM_NDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PLL_SYSTEM_XDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.10 PLL_SYSTEM_MDIV_42_5 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4
I2Sout_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1 5.4.2 5.4.3 5.4.4 OUTPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM_DIV : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCM_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PCM_CROSS : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5
GPSO_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 25
5.5.1 5.5.2 OUTPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 GPSO_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6
I2Sin_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . 27
5.6.1 5.6.2 5.6.3 5.6.4 INPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I_AUDIO_CONFIG_1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I_AUDIO_CONFIG_2 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I_AUDIO_CONFIG_3 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7
SDI_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . . 29
5.7.1 5.7.2 5.7.3 POL_REQ : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 INPUT_CONF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I_AUDIO_CONFIG_1 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8
COMMAND registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8.1 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 SOFT_RESET : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CK_CMD : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DEC_SEL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RUN : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CRC_IGNORE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MUTE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SKIP : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PAUSE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.9
STATUS registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.9.1 5.9.2 STATUS_MODE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STATUS_CHANS_NB : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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5.9.3 5.9.4 5.9.5 STATUS_SF : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STATUS_FE : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 HEADER _n: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.10
MIX_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . . . 34
5.10.1 MIX_MODE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.10.2 MIX_DLA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10.3 MIX_DLB: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10.4 MIX_DRA: 5.10.5 MIX_DRB: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.11
TONE_CONFIGURATION registers description . . . . . . . . . . . . . . . . . . . . . . 36
5.11.1 TONE_ON: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.11.2 TONE_FCUTH : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.11.3 TONE_FCUTL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.11.4 TONE_GAINH : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.11.5 TONE_GAINL : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.11.6 TONE_GAIN_ATTEN : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7
I/O CELL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 7.2 7.3 7.4 7.5 7.6 TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control . . 41 TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control 41 TTL Schmitt Trigger Inpud Pad Buffer, 3V capable . . . . . . . . . . . . . . . . . . . . 41 TTL Inpud Pad Buffer, 3V capable with Pull-Up . . . . . . . . . . . . . . . . . . . . . . 41 TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable 42 TTL Input Pad Buffer, 3V capable, with pull down . . . . . . . . . . . . . . . . . . . . . 42
8 9
Package Informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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1 Typical application circuit and block diagram
1
1.1
Typical application circuit and block diagram
Block diagram
Figure 1. Block diagram
BSO_LRCK SDO I/F BSI_BCK BSI_DATA DREQ BCKI SDI LRCKI I2S IN I/F MMDSP CORE SBC CODEC SDI I/F BSO_DATA BSO_BCK GPSO_CK GPSO I/F GPSO_SDO GPSO_REQ
INPUT BUFFER
BCKO PCM OUTPUT BUFFER I2S OUT I/F SDO LRCKO
RQST
AUDIO PLL
SCL SDA
I2C I/F
I2C REG BANK
SYSTEM PLL
OSC
OSCK
XTI
XTO
D05AU1615
1.2
Typical bluetooth wireless audio application
Figure 2. Transmitter block diagram
ENCODER
L ADC R I S IN I/F
2
SDO I/F
BT MODULE
STA027
D05AU1616
Figure 3.
Receiver block diagram
DECODER
BT MODULE SDI I/F I S OUT I/F
2
L DAC R
STA027
D05AU1617
Note:
for Bluetooth chipset please refer to following device: SLTLC2416, STLC2150, STLC2500. For ADC and DAC solutions please refer to following devices: STW5094, STW5095, TDA7535.
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2 Pins description and connection diagram
STA027
2
2.1
Table 1.
PIN
Pins description and connection diagram
Pin description
pin description
Pin Name Type Description Source/Dest
SDO interface 1 2 3 SDI interface 4 7 8 9 DREQ BSI_LRCK BSI_BCK BSI_DATA O I I I Bitstream data request Bitstream interface left/right Clock Bitstream interface clock Bitstream interface serial data To MCU From MCU From MCU From MCU BSO_LRCK BSO_BCK BSO_DATA I I I DSP Interface left/right Clock DSP interface serial data DSP interface bit clock From DSP From DSP From DSP
PCM IN interface 12 13 14 LRCKI BCKI SDI I I I ADC left/right Clock ADC bit clock ADC serial data From ADC From ADC From ADC
PCM OUT interface 19 20 21 22 GPSO interface 54 55 56 GPSO_SDO GPSO_CK GPSO_REQ O I O GPSO serial data GPSO bit clock GPSO request signal To MCU From MCU To MCU OSCK LRCKO BCKO SDO O O O O DAC oversampling clock DAC Interface left/right Clock DAC bit clock DAC serial data To DAC/ADC To DAC To DAC To DAC
GPIO interface 26 27 28 31 32 33 IODATA0 IODATA1 IODATA2 IODATA3 IODATA4 IODATA5 I/O I/O I/O I/O I/O I/O GPIODATA0 GPIODATA1 GPIODATA2 GPIODATA3 GPIODATA4 GPIODATA5
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Table 1.
PIN 34 35 44 45 46 47 48 49 50 51
2 Pins description and connection diagram
pin description
Pin Name IODATA6 IODATA7 IODATA8 IODATA9 IODATA10 IODATA11 IODATA12 IODATA13 IODATA14 IODATA15 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIODATA6 GPIODATA7 GPIODATA8 GPIODATA9 GPIODATA10 GPIODATA11 GPIODATA12 GPIODATA13 GPIODATA14 GPIODATA15 Description Source/Dest
HANDSHAKE SIGNALS 59 60 I2C LINK 63 64 SCL SDA I I/O I2C clock signal I2C data signal From MCU To MCU RQST STB O I I2C data signal Strobe signal To MCU From MCU
MISCELLANEOUS 15 16 17 18 25 38 40 -RESET -TESTEN XTI XTO CLKOUT FILT1 FILT0 I I I I O O Reset Reserved for test purpose Oscillator input Oscillator output Buffered output clock PLL external filter PLL external filter
POWER SUPPLY 5 6 10 11 23 24 29 30 VDD_1 VSS_1 VDD_2 VSS_2 VCC_1 VSS_3 VDD_3 VSS_4 Digital supply (2.5V Power Supply) Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Digital supply (2.5V Power Supply) Ground
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STA027
Table 1.
PIN 36 37 39 41 42 43 52 53 57 58 61 62
pin description
Pin Name VDD_4 VSS_5 PLL_VCC PLL_GND VCC_2 VSS_6 VSS_7 VDD_5 VSS_8 VCC_3 VSS_9 VDD_6 Type Description Digital supply (2.5V Power Supply) Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Ground Digital supply (2.5V Power Supply) Ground Digital supply (3.3V Power Supply) Ground Digital supply (2.5V Power Supply) Source/Dest
Figure 4.
GPSO_REQ GPSO_SDO IODATA15 IODATA14 IODATA13 GPSO_CK
VCC_3
VDD_6
VDD_5
VSS_8
VSS_9
SDA
SCL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BSO_LRCK BSO_BCK BSO_DATA DREQ VDD_1 VSS_1 BSI_LRCK BSI_BCK BSI_DATA VDD_2 VSS_2 LRCK1 BCKI SDI RESET TESTEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SDO VCC_1 VSS_3 CLKOUT IODATA0 IODATA1 IODATA2 VDD_3 VSS_4 IODATA3 IODATA4 XTI XTO LRCKO BCKO OSCK
STB
VSS_7
RQST
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IODATA12 IODATA11 IODATA10 IODATA9 IODATA8 VSS_6 VCC_2 PLL_GND FILT0 PLL_VCC FILT1 VSS_5 VDD_4 IODATA7 IODATA6 IODATA5
D00AU1227
Table 2.
Symbol Rth j-amb
Thermal Data
Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W
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3 Electrical Specification
3
3.1
Electrical Specification
Absolute maximum ratings
Table 3.
Symbol VDD VCC PLL-VCC VIH/VIL Tstg Top Tj
Absolute Maximum Ratings
Parameter Digital Power Supply at 2.5V (nominal) Digital Power Supply at 3.3V (nominal) Analog Supply Voltage at 2.5V (nominal) Voltage on input pins (3.3V pads) Storage Temperature Operative ambient temp Operating Junction Temperature Value -0.5 to 3.3 -0.5 to 4 -0.5 to 3.3 -0.5 to VCC +0.5 -40 to +150 -40 to +85(*) -40 to 125 Unit V V V V C C C
3.2
Electrical characteristics
(Tamb = 25C; Rg = 50 unless otherwise specified) Table 4.
Symbol VDD VCC Power Supply Voltage Power Supply Voltage
DC Operating Conditions
Parameter Value 2.5 0.25 3.3 0.3 2.5 0.25 Unit V V V
PLL_VCC Power Supply Voltage
Table 5.
Symbol IIL IIH Vesd
General Interface Electrical Characteristics
Parameter Low Level Input CurrentWithout pullup device Test Condition Vi = 0V Min. -10 -10 2000 Typ. Max. 10 10 Unit A A V Note 1 1 2
High Level Input CurrentWithout pullVi = VDD up device Electrostatic Protection Leakage < 1A
Note: 1 The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. 2 Human Body Model.
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3 Electrical Specification
STA027
Table 6.
Symbol VIL VIH Vol Voh
DC electrical characteristics
Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = Xma 0.85*VCC 0.8*VCC 0.4V Test Condition Min. Typ. Max. 0.2*VCC Unit V V V V 1, 2 1, 2 Note
Note: 1 Takes into account 200mV voltage drop in both supply lines. 2 X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Table 7.
Symbol Ipu Rpu Parameter Pull-up current Equivalent Pull-up Resistance Test Condition Vi = 0V; pin numbers 7, 24 and 26 Min. -25 Typ. -66 50 Max. -125 Unit A k Note 1
Note: 1 Min. condition: VDD = 2.7V, 125C Min process Max. condition: VDD = 3.6V, -20C Max. Table 8.
Symbol
Power Dissipation
Parameter Power Dissipation@ VDD = 2.4V Test Condition Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz Min. Typ. 165 170 185 Max. Unit mW mW mW Note
PD
Note:
power measurements refer to encoder mode.
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4 Host register
4
Host register
The following table gives a description of STA027 register list. The STA027 device includes 256 I2C registers. In this document, only the user-oriented registers are described. The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read or written :

DWT : During Whole Time (at any time during process). DEC : During External Config (period between RUN=2 and RUN=1). DBO : During Boot (period between RUN=0 and RUN=2). ABO : After BOot (period after RUN=1). AEC : After External Config (period after RUN=2). EDF : Every Decoded Frame (each time a frame has been decoded). EDB : Every Decoded Block (each time a block has been decoded).
Figure 5.
SOFT_RESET = 1 CK_CMD = 0 block1 frame1 block2 frame1 block1 frame2
HR
RUN==0
RUN==2
RUN==1
time
DWT DBO DEC ABO AEC
D01AU1260
EDB
EDB EDF
EDB
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4 Host register
STA027
4.1
Table 9.
Register map
register map by function
Hex 0x00 Dec 0 1 211 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 102 103 104 105 102 106 90 91 92 93 VERSION IDENT SOFT_VERSION PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 OUTPUT_CONF PCM_DIV PCM_CONF PCM_CROSS OUTPUT_CONF GPSO_CONF INPUT_CONF I_AUDIO_CONFIG_1 I_AUDIO_CONFIG_2 I_AUDIO_CONFIG_3 Name Type RO RO RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW When DWT DWT DWT DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC Register function
VERSION
0x01 0xD3 0xDC 0xDD 0xDE 0xDF 0xE0
PLL_AUDIO_CONFIGURATION 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA PLL_SYSTEM_CONFIGURATION 0xEB 0xEC 0xED 0xEE 0xEF 0x66 I2Sout_CONFIGURATION 0x67 0x68 0x69 0x66 GPSO_CONFIGURATION 0x6A 0x5A I2Sin_CONFIGURATION 0x5B 0x5C 0x5D
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Table 9. register map by function
Hex 0x59 SDI_CONFIGURATION 0x5A 0x5B 0x10 0x3A 0x55 0x56 COMMAND 0x52 0x53 0x57 0x58 0xCC 0xCD 0xCE 0x6F 0xD4 STATUS 0xD5 0xD6 0xD7 0xD8 0xD9 0x7b 0x7c MIX_CONFIGURATION 0x7d 0x7e 0x7f 0x75 0x76 0x77 TONE_CONFIGURATION 0x78 0x79 0x7A 120 121 122 TONE_GAINH TONE_GAINL TONE_GAIN_ATTEN 213 214 215 216 217 123 124 125 126 127 117 118 119 HEADER_2 HEADER_3 HEADER_4 HEADER_5 HEADER_6 MIX_MODE MIX_DLA MIX_DLB MIX_DRA MIX_DRB TONE_ON TONE_FCUTH TONE_FCUTL 82 83 87 88 204 205 206 111 212 CRC_IGNORE MUTE SKIP PAUSE STATUS_MODE STATUS_CHAN_NB STATUS_SF STATUS_FE HEADER_1 Dec 89 90 91 16 58 85 86 POL_REQ INPUT_CONF I_AUDIO_CONFIG_1 SOFT_RESET CK_CMD DEC_SEL RUN Name
4 Host register
Register function
Type RW RW RW WO WO RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW RW RW RW RW
When DEC DEC DEC DWT DBO DEC DEC ABO ABO ABO ABO EDF EDF EDF EDF EDF EDF EDF EDF EDF EDF ABO ABO ABO ABO ABO ABO ABO ABO ABO ABO ABO
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5 Register description
STA027
5
5.1
5.1.1
Register description
Version registers description
VERSION :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x00 (0) Type : RO - DWT Software Reset : 0x10 Hardware Reset : 0x10
Description : The VERSION register is Read-only and it is used to identify the IC on the application board.
5.1.2
IDENT :
b7 1 b6 0 b5 1 b4 0 b3 1 b2 1 b1 0 b0 0
Address : 0x01 (1) Type : RO - DWT Software Reset : 0xAC Hardware Reset : 0xAC
Description : IDENT is a read-only register and it is used to identify the IC on an application board. IDENT always has the value 0xAC.
5.1.3
SOFT_VERSION :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xD3 (211) Type : RO - DWT Software Reset : X Description : The SOFT_VERSION register is Read-only and it is used to identify the software running on the IC.
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5 Register description
5.2
5.2.1
PLL_AUDIO_CONFIGURATION registers description
PLL_AUDIO_PEL_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDC (220) Type : RW - DEC Software Reset : 58
Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. ofact is the oversampling factor needed by the DAC (ofac==246 or ofac==384). Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.2
PLL_AUDIO_PEH_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDD (221) Type : RW - DEC Software Reset : 187
Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.3
PLL_AUDIO_NDIV_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDE (222) Type : RW - DEC Software Reset : 0
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5 Register description
STA027
Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.4
PLL_AUDIO_XDIV_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xDF (223) Type : RW - DEC Software Reset : 3
Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.5
PLL_AUDIO_MDIV_192 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE0 (224) Type : RW - DEC Software Reset : 12
Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*192 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
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5 Register description
5.2.6
PLL_AUDIO_PEL_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE1 (225) Type : RW - DEC Software Reset : 54
Description : This register must contain a PEL value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - fact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.7
PLL_AUDIO_PEH_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE2 (226) Type : RW - DEC Software Reset : 118
Description : This register must contain a PEH value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.8
PLL_AUDIO_NDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE3 (227) Type : RW - DEC Software Reset : 0
Description : This register must contain a NDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3.
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5 Register description
STA027
Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.9
PLL_AUDIO_XDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE4 (228) Type : RW - DEC Software Reset : 2
Description : This register must contain a XDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1, 2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.2.10 PLL_AUDIO_MDIV_176 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE5 (229) Type : RW - DEC Software Reset : 8
Description : This register must contain a MDIV value that enables the audio PLL to generate a frequency of ofact*176 kHz for the PCMCK.See table 1,2 & 3. Default value at soft reset assume : - - ofact == 256 external crystal provide a CRYCK running at 14.31818 MHz
5.3
5.3.1
PLL_SYSTEM_CONFIGURATION registers description
PLL_SYSTEM_PEL_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE6 (230)
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Type : RW - DEC Software Reset : 0
5 Register description
Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.2
PLL_SYSTEM_PEH_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE7 (231) Type : RW - DEC Software Reset : 0
Description : This register must contain a PEH value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.3
PLL_SYSTEM_NDIV_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE8 (232) Type : RW - DEC Software Reset : 0
Description : This register must contain a NDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
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5 Register description
STA027
5.3.4
PLL_SYSTEM_XDIV_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE9 (233) Type : RW - DEC Software Reset : 1 Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 50 MHZ for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.5
PLL_SYSTEM_MDIV_50 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xEA (234) Type : RW - DEC Software Reset : 13
Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 50 MHz for the SYSCK. See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.6
PLL_SYSTEM_PEL_42_5
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE6 (230) Type : RW - DEC Software Reset : 126
Description : This register must contain a PEL value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
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5 Register description
5.3.7
PLL_SYSTEM_PEH_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE7 (231) Type : RW - DEC Software Reset : 223
Description : This register must contain a PEH value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.8
PLL_SYSTEM_NDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE8 (232) Type : RW - DEC Software Reset : 0
Description : This register must contain a NDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.3.9
PLL_SYSTEM_XDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xE9 (233) Type : RW - DEC Software Reset : 1
Description : This register must contain a XDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
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5 Register description
STA027
5.3.10 PLL_SYSTEM_MDIV_42_5 :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xEA (234) Type : RW - DEC Software Reset : 10
Description : This register must contain a MDIV value that enables the system PLL to generate a frequency of 42.5 MHz for the SYSCK.See table 4. Default value at soft reset assume : - external crystal provide a CRYCK running at 14.31818 MHz
5.4
5.4.1
I2Sout_CONFIGURATION registers description
OUTPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x66 (102) Type : RW - DEC Software Reset : 0
Description : If set to 1 enable the configurability of the PCM-BLOCK Output thanks to following registers, else disable this configurability and take embedded default configuration for PCM-BLOCK registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : - - - PCM_DIV = 3; PCM_CONF = 0; PCM_CROSS = 0;
5.4.2
PCM_DIV :
b7 0 b6 0 b5 DV5 b4 DV4 b3 DV3 b2 DV2 b1 DV1 b0 DV0
Address : 0x67 (103) Type : RW - DEC
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Software Reset : 0
5 Register description
Description : If OUTPUT_CONF == 1, configure the divider to generate the bit clock of the I2Sout interface, called BCK0, from PCMCK. according the following relation : BCKO = PCMCK / 2 * (PCM_DIV+1)
5.4.3
PCM_CONF :
b7 0 b6 CO6 b5 CO5 b4 CO4 b3 CO3 b2 CO2 b1 CO1 b0 CO0
Address : 0x68 (104) Type : RW - DEC Software Reset : 0
Description : If OUTPUT_CONF == 1, configure the I2Sout interface according following table Table 10. .
Comment 0 : 16 bits mode (16 slots transmitted). 1 : 18 bits mode (18 slots transmitted). 2 : 20 bits mode (20 slots transmitted). 3 : 24 bits mode (24 slots transmitted). Polarity of BCKO : 0 : data are sent on the falling edge & stable on the rising). 1 : (data are sent on the rising edge & stable on the falling). 0 : I2S format is selected 1 : other format is selected Polarity of LRCKO : 0 : low->right, high->left). 1 : low->left, high->right so compliant to I2S format ). 0 : data are in the last BCKO cycles of LRCKO (right aligned data). 1 : data are in the first BCKO cycles of LRCKO (left aligned data). 0 : the transmission is LS bit first. 1 : the transmission is MS bit first.
Bit fields
CO[1:0]
CO2
CO3
CO4
CO5 CO6
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5 Register description
STA027
5.4.4
PCM_CROSS :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 CR1 b0 CR0
Address : 0x69 (105) Type : RW - DEC Software Reset : 0
Description : If OUTPUT_CONF == 1, CR[1:0] is used to configure the output crossbar according following table Table 11.
CR1 0 0 1 1
.
CR0 0 1 0 1 Comment Left channel is mapped on the left output. Right channel is mapped on the right output. Left channel is duplicated on both output channels. Right channel is duplicated on both output channels. Right and left channels are toggled.
5.5
5.5.1
GPSO_CONFIGURATION registers description
OUTPUT_CONF :
b7 X b6 X b5 X b4 X b3 X b2 0C2 b1 OC1 b0 OC0
Address : 0x66 (102) Type : RW - DEC Software Reset : 0
Description Table 12.
Bit fields Comment Configuration of gpso : 0 : take embedded default configuration. 1 : configure gpso from register GPSO_CONF.
OC0
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Table 12.
Bit fields Comment
5 Register description
OC1
Use of block PCM to generate clocks (PCMCK, LRCK & BCK): 0 : no use. 1 : use it. Configuration of PCM block: 0 : take embedded default configuration. 1 : configure PCM block from PCM_DIV & PCM_CONF registers.
OC2
Note:
that embedded default configuration for GPSO can be retrieved by user thanks to following setting : - GPSO_CONF = b00000011; that embedded default configuration for PCM block is described at previous chapter.
Note:
5.5.2
GPSO_CONF :
b7 CF7 b6 CF6 b5 CF5 b4 CF4 b3 CF3 b2 CF2 b1 CF1 b0 CF0
Address : 0x6A (106) Type : RW - DEC Software Reset : 0
Description : If OUTPUT_CONF == 1, this register configure the GPSO interface Table 13. .
Comment Polarity of GPSO_CK : 0 : data provided on rising edge & stable on falling edge 1 : data provided on falling edge & stable on rising edge Polarity of GPSO_REQ : 0 : data are valid when GPSO_REQ is high 1 : data are valid when GPSO_REQ is low Reserved : to be set to 0.
Bit fields
CF0
CF1 CF[7:2]
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5 Register description
STA027
5.6
5.6.1
I2Sin_CONFIGURATION registers description
INPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x5A (90) Type : RW - DEC Software Reset : 0
Description : If set to 1 enable the configurability of the I2Sin Input thanks to following registers, else disable this configurability and take embedded default configuration for I2Sin registers. Note that this embedded default configuration can be retrieved by user thanks to following setting : - - - I_AUDIO_CONFIG_1 = b00000110; I_AUDIO_CONFIG_2 = b11100000; I_AUDIO_CONFIG_3 = b00000001;
5.6.2
I_AUDIO_CONFIG_1:
b7 CF7 b6 CF6 b5 CF5 b4 CF4 b3 CF3 b2 CF2 b1 CF1 b0 CF0
Address : 0x5B (91) Type : RW - DEC Software Reset : 0
Description : If INPUT_CONF == 1, this register configure the I2Sin interface. Table 14.
Bit fields Comment Relative synchro : 0 : synchro with first data bit 1 : synchro one bit before first data bit Data reception configuration : 0 : LSB first 1 : MSB first Polarity of bit clock BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge
CF0
CF1
CF2
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Table 14.
Bit fields Polarity of LR clock LRCK : 0 : negative 1 : positive Comment
5 Register description
CF3
CF4 CF[7:5]
Start value of LRCK : combined with CF3, this bit enable user to determine left/right couple according to the following table. Reserved : to be set to 0.
Table 15.
CF3 0 1 0 1 CF4 0 0 1 1 Left/Right couples (data1/data2), (data3/data4),... (data0/data1), (data2/data3),... (data0/data1), (data2/data3),... (data1/data2), (data3/data4),...
5.6.3
I_AUDIO_CONFIG_2 :
b7 LR7 b6 LR6 b5 LR5 b4 LR4 b3 LR3 b2 LR2 b1 LR1 b0 LR0
Address : 0x5C (92) Type : RW - DEC Software Reset : 0
Description : See I_AUDIO_CONFIG_3 register description..
5.6.4
I_AUDIO_CONFIG_3 :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 LR9 b0 LR8
Address : 0x5D (93) Type : RW - DEC Software Reset : 0
Description : If INPUT_CONF == 1, this register is used to configure the phase of the LRCK of the I2Sin.
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5 Register description
STA027
Table 16.
Bit fields Comment Position of the data within the LRCK phase : - if CF1 = 0 (LSB), value must be set to[31 - SL[9:5] - bit position of the first bit of data within the LRCK phase]. LR[4:0] - if CF1 = 1 (MSB), value must be set to bit position of the first bit of data within the LRCK phase.
Note:
LR[9:5] LR[15:10]
that range of value for this bit position is [0:31].
Length-1 of the data. Max value is 31. Reserved : to be set to 0
5.7
5.7.1
SDI_CONFIGURATION registers description
POL_REQ :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x59 (89) Type : WO - DEC Software Reset : 0
Description : This register manage the polarity of the data REQ signal DREQ of the BS input interface. If set to 0, data are requested when REQ = 0. If set to 1, data are requested when REQ = 1.
5.7.2
INPUT_CONF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x5A (90) Type : RW - DEC Software Reset : 0
Description : If set to 1 enable the configurability of the BSB input interfaces in burst mode thanks to following register, else disable this configurability and take embedded default configuration. Note that this embedded default configuration can be retrieved by user thanks to following setting : -
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I_AUDIO_CONFIG1 = b00000000;// polarity choice
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5 Register description
5.7.3
I_AUDIO_CONFIG_1 :
b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 CF0
Address : 0x5B (91) Type : RW - DEC Software Reset : 0
Description : If INPUT_CONF == 1, this register is used to configure BSB bit clock Table 17.
Bit
.
Comment Polarity of bit clock BS_BCK : 0 : data provided on falling edge & stable on rising edge. 1 : data provided on rising edge & stable on falling edge.
CF0
5.8
5.8.1
COMMAND registers description
SOFT_RESET :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x10 (16) Type : WO - DWT Software Reset : 0
Description : When user write 1 in this register, a soft reset occurs. The core command register and the interrupt register are cleared. The decoder goes into idle mode.
5.8.2
CK_CMD :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x3A (58) Type : WO - DBO Software Reset : 1 Hardware Reset : 1
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5 Register description
STA027
Description : After a soft reset, user must write 0 in CK_CMD to run the core clock of the chip. This will begin the boot of the chip, and so get it out of its idle state.
5.8.3
DEC_SEL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x55 (85) Type : RW - DEC Software Reset : 0
Description : This register select the encoder/decoder data flux according the mode written in following table Table 18. .
Bit(7:0) 10 18 19 21 22 Mode SINE (test mode chip alive) SBC decoder ADC/GPSO SBC encoder SDI/GPSO SBC encoder ADC/SDO SBC encoder
Note:
available modes depends on patch code used
5.8.4
RUN :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x56 (86) Type : RW - DEC Software Reset : 0
Description : - - - When a software reset occurs, register RUN is reset (value 0) by the dsp (see I). When boot routines are finished, the dsp write inside RUN register the value 2 : this is the start of the external configuration period (start of DEC : see I). When the external device wants to end the external configuration period, it must write the value 1 inside the register RUN: this is the run command that starts the decoding process (see I).
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5 Register description
5.8.5
CRC_IGNORE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x52 (82) Type : RW - ABO Software Reset : 0
Description : For decoders having CRC abilities (see each decoder configuration), if set to 0 enable the check of CRC, if set to 1 disable the check of the CRC.
5.8.6
MUTE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x53 (83) Type : RW - ABO Software Reset : 0
Description : For decoders having MUTE abilities (see each decoder configuration), if set to 0 disable the mute of the decoder, if set to 1 enable the mute of the decoder. Note that during a MUTE the input stream keeps on entering.
5.8.7
SKIP :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x57 (87) Type : RW - ABO Software Reset : 0
Description : For data flux using USSB Input, if SKIP == n>2, decoder skip (n-1) out of n frames. Note that maximum value for n is 8, and if n==0 or n==1, no frames is skipped.
5.8.8
PAUSE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x58 (88)
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5 Register description
STA027
Type : RW - ABO Software Reset : 0
Description : For decoders having PAUSE abilities (see each decoder configuration), if set to 0 disable the pause of the decoder, if set to 1 enable the pause of the decoder. Note that during a PAUSE the input stream is stopped.
5.9
5.9.1
STATUS registers description
STATUS_MODE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCC (204) Type : RO - EDF Software Reset : 0 Description : This register give the type of the currently decoded bitstream.
5.9.2
STATUS_CHANS_NB :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCD (205) Type : RO - EDF Software Reset : 0
Description : This register gives the number of channel currently decoded.
5.9.3
STATUS_SF :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xCE (206) Type : RO - EDF Software Reset : 0
Description :
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5 Register description
This register gives the index of the sampling frequency of the stream currently decoded. Note that sampling frequency indexes are given by table 5
5.9.4
STATUS_FE :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x6F (111) Type : RO - AEC Software Reset : 0
Description : This register give the status of the synchronization process according following table. Table 19.
Value 0 1 2 3 Syncrho not started Syncword found Syncword search Syncword hard to find Level
5.9.5
HEADER _n:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0xD4 (212) to 0xD9 (217) Type : RO - EDF Software Reset : 0
Description : This register give the nth byte of the header of the frame currently decoded
5.10
MIX_CONFIGURATION registers description
5.10.1 MIX_MODE:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7B (123) Type : RW - ABO Software Reset : 2
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5 Register description
STA027
Description : This register selectes the mode of mix/volume control Table 20. :
Value 0 1 2 3 diseable mix/volume control volume control mono to stereo (up-mix) stereo to mono (down-mix) Mode
5.10.2 MIX_DLA:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7C (124) Type : RW - ABO Software Reset : 0
Description : This register specifies the direct left attenuation (in dB).
5.10.3 MIX_DLB:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7D (125) Type : RW - ABO Software Reset : 0
Description : This register specifies the left attenuation (in dB) on rigth channel.
5.10.4 MIX_DRA:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7E (126) Type : RW - ABO Software Reset : 0
Description : This register specifies the direct right attenuation (in dB).
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5 Register description
5.10.5 MIX_DRB:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7F (127) Type : RW - ABO Software Reset : 0
Description : This register specifies the rigth attenuation (in dB) on left channel.
5.11
TONE_CONFIGURATION registers description
5.11.1 TONE_ON:
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x75 (117) Type : RW - ABO Software Reset : 0
Description : This register enables/diseables (1/0) the tone control.
5.11.2 TONE_FCUTH :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x76 (118) Type : RW - ABO Software Reset : 20
Description : This register specifies the high cut frequency: fcut(in Hz)=(TONE_FCUTH+1)*50.
5.11.3 TONE_FCUTL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x77 (119) Type : RW - ABO Software Reset : 10
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5 Register description
STA027
Description : This register specifies the low cut frequency: fcut(in Hz) = (TONE_FCUTL+1)*10
5.11.4 TONE_GAINH :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x78 (120) Type : RW - ABO Software Reset : 12
Description : This register specifies the gain on high frequencies: gain(in Db)=(TONE_GAINH-12)*1.5
5.11.5 TONE_GAINL :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x79 (121) Type : RW - ABO Software Reset : 12
Description : This register specifies the gain on high frequencies: gain (in Db)=(TONE_GAINL-12)*1.5. Value of register from 0 to 24.
5.11.6 TONE_GAIN_ATTEN :
b7 b6 b5 b4 b3 b2 b1 b0
Address : 0x7A (122) Type : RW - ABO Software Reset : 0
Description : This register specifies the attenuation on global spectrum: gain (in dB)=TONE_GAIN_ATTEN*1.5. Value of register from 0 to 12.
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6 TABLES
6
TABLES
Table 21. values to configure audio PLL for ofact==256.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 256*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 42 169 0 3 18 56 16 0 3 17 CRYCK in MHz 14.31818 58 187 0 3 12 54 118 0 2 8 CRYCK in MHz 14.7456 85 85 0 0 2 0 64 0 3 11
Table 22.
values to configure audio PLL for ofact==384
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 384*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 224 190 0 1 13 42 140 0 1 12 CRYCK in MHz 14.31818 108 76 0 1 9 54 118 0 1 8 CRYCK in MHz 14.7456 0 0 0 1 9 0 48 0 1 8
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6 TABLES
STA027
Table 23. values to configure audio PLL for ofact==512.
This table give values to configure the audio PLL according CRYCK so that to generate a PCMCK == 512*SF.
Register PLL_AUDIO_PEL_192 PLL_AUDIO_PEH_192 PLL_AUDIO_NDIV_192 PLL_AUDIO_XDIV_192 PLL_AUDIO_MDIV_192 PLL_AUDIO_PEL_176 PLL_AUDIO_PEH_176 PLL_AUDIO_NDIV_176 PLL_AUDIO_XDIV_176 PLL_AUDIO_MDIV_176 CRYCK in MHz 10 42 169 0 1 18 56 16 0 1 17 CRYCK in MHz 14.31818 58 187 0 0 5 157 157 0 1 11 CRYCK in MHz 14.7456 85 85 0 1 12 0 64 0 1 11
Table 24.
values to configure system PLL for SYSCK.
This table give values to configure the system PLL according CRYCK so that to generate a SYSCK == 50MHz. or SYSCK == 42.5MHz.
Register PLL_SYSTEM_PEL_50 PLL_SYSTEM_PEH_50 PLL_SYSTEM_NDIV_50 PLL_SYSTEM_XDIV_50 PLL_SYSTEM_MDIV_50 PLL_SYSTEM_PEL_42_5 PLL_SYSTEM_PEH_42_5 PLL_SYSTEM_NDIV_42_5 PLL_SYSTEM_XDIV_42_5 PLL_SYSTEM_MDIV_42_5 CRYCK in MHz 10 162 11 0 1 19 0 0 0 1 16 CRYCK in MHz 14.31818 0 0 0 1 13 126 223 0 1 10 CRYCK in MHz 14.7456 28 152 0 1 12 100 135 0 1 10
Table 25.
index of the Sampling Frequency
Index 0 1 2 4 5 Frequency 48 kHz 44.1 kHz 32 kHz 96 kHz 88.2 kHz
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Table 25. index of the Sampling Frequency
Index 6 8 9 10 12 13 14 16 17 18 3, 7, 11, 15 or 19 Frequency 64 kHz 24 kHz 22.05 kHz 16 kHz 12 kHz 11.025 kHz 8 kHz 192 kHz 176.4 kHz 128 kHz illegal frequency
6 TABLES
6.1
Notations
ABO : After BOot (see I). AEC : After External Config (see I). BCK: Bit ClocK BSA: BitStream input interface in Audio mode. BSB: BitStream input interface in Burst mode. BS: BitStream input interface. BYPASSA : decoder BYPASS an Audio stream. CD : input interface for CD. CK : ClocK. CRYCK: CRYstal ClocK provided to the chip by an external crystal. DBO : During BOot (see I). DEC : During External Config (see I). DWT : During Whole Time (see I). EDB : Every Decoded Block (see I). EDF : Every Decoded Frame (see I). LRCK: Left Right ClocK for an I2S interface. ofact: oversampling factor for PCMCK (PCMCK == ofact * SF). PCMCK: PCM ClocK (can be generated by the audio PLL). SF: Sampling Frequency. SYSCK: SYStem ClocK (clock of the core, can be generated by the system PLL). X : don't care.
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7 I/O CELL DESCRIPTION
STA027
7
7.1
I/O CELL DESCRIPTION
TTL Tristate Output Pad Buffer, 3V capable 4mA, with Slew Rate Control
Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59
EN Z A
D98AU904
INPUT PIN Z
MAX LOAD 100pF
7.2
TTL Schmitt Trigger Bidir Pad Buffer, 3V capable, 4mA, with Slew Rate Control
Pin numbers: 1, 2, 3, 7, 8, 9, 19
EN IO A
INPUT PIN IO
CAPACITANCE TBD
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D98AU905
7.3
TTL Schmitt Trigger Inpud Pad Buffer, 3V capable
Pin numbers:17, 60, 63
EN
INPUT PIN
IO A
CAPACITANCE TBD
A
D98AU905
ZI
7.4
TTL Inpud Pad Buffer, 3V capable with Pull-Up
Pin numbers:15, 16
INPUT PIN
A Z
CAPACITANCE TBD
A
D98AU907
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7.5
TTL Schmitt Trigger Bidir Pad Buffer, with Pull-up, 4mA, with slew rate control / 3V capable
Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64
EN IO A
INPUT PIN IO
CAPACITANCE TBD
OUTPUT PIN IO
MAX LOAD 100pF
ZI
D00AU1150
7.6
TTL Input Pad Buffer, 3V capable, with pull down
Pin numbers: 12, 13, 14, 55
A Z
INPUT PIN A
CAPACITANCE TBD
D00AU1222
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8 Package Informations
STA027
8
Figure 6.
Package Informations
TQFP64 (10x10x1.4mm) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 12.20 10.20 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch
OUTLINE AND MECHANICAL DATA
0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.480 0.401
0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031
TQFP64 (10 x 10 x 1.4mm)
D D1 A D3 A1 48 49 33 32
0.08mm ccc Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
0051434 E
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9 Revision history
9
Revision history
Date 1-sept-2005 Revision 1 Initial release. Changes
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STA027
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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